Professor Michael Flynn, University of Michigan As an example it was critical to our success in digital-dominant frac-N PLLs." "CppSim has become our 'go-to' tool for investigating new PLL architectures. Co-simulation with Spectre validates the behavioral models against device-level implementations." Further, the embedding of Vppsim modules within Cadence AMS allows for flexible functional debugging of the architecture using more detailed Verilog implementations. The signal outputs sampled at constant rate are easily probed for powerful post-processing within Matlab. Schematic descriptions work naturally and intuitively for architectural enhancements. The rich C++ class set of CppSim allows easy implementation of a multiplicity of alternative architectures. CppSim simulation of C++ modules runs very fast while still including key relevant timing details. "Vppsim within the Cadence environment has been the tool of choice at PhaseLink for the evaluation of advanced PLL synthesizer architectures. Matthew Straayer, Cambridge Analog Technologies (CAT)
Cpusim git verification#
The unique combination of simulation speed, timing accuracy, flexibility, and digital verification capability that CppSim/VppSim offers as a supplement to the traditional EDA design flow is a great asset for our designers." "Cambridge Analog Technologies (CAT) has found CppSim / VppSim to be very useful in the design of high-performance mixed-signal IP, such as low-jitter digital PLL and low-power high-resolution ADC.We found it to be the shortest path to design all-digital PLLs as well."Įmad Hegazi, General Manager RF/AMS SySDSoft Inc We were able to build multiple Fractional-N PLL synthesizers and optimize their performance in short times using CppSim. Its phenomenal speed advantage and ease of use make it an indispensable tool for frequency synthesizers and CDR designers. I used all versions of this fantastic tool as well as its Verilog-AMS compatible version, VppSim.
Cpusim git full#
Given its full compatibility with the Cadence environment, co-sim ability with Verilog, use of analogLib-style primitives, and its fast learning curve, CppSim has become our system simulation tool of choice to evaluate innovative mixed-signal architectures going well beyond PLL circuits."įred S. CppSim, on the other hand, provides fast, accurate, and headache-free transient noise simulation results with relative ease.
Cpusim git code#
Verilog-A is also an option, but writing Verilog-A code to optimize for speed, accurate noise modeling and error-free simulations is challenging.
Links typically require simulation of long bit sequences in order to capture intersymbol interference effects and examine loop dynamics which are typically orders of magnitude slower than the symbol rate. "CppSim/VppSim is a great tool for high-speed link applications to achieve both fine timing accuracy and speed when capturing interactions between adaptive equalization algorithms and clock-and-data-recovery loops.
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